The present invention relates generally to an Integrated Circuit (IC) design, and in particular, to a method and system for estimating the power consumption of the IC.
In recent years, power has become a key design metric for System-on-Chip (SOC) designs implemented in deep sub-micron (DSM) technologies. There are several known methods for estimating the power consumption of SOCs. Accurate power estimation is essential for minimizing the power consumption of a circuit. Power estimation is also needed for various functions, such as in the process of designing a robust power grid. Moreover, accurate power estimation of parameterized reusable circuits (also known as cores or intellectual property (IP) cores) is required at the early stages of the analyses, to analyze power versus performance trade offs among the different components.
Commonly used power estimation methodologies include both analytical and simulation methods. In the analytical method, the power consumption of the circuit is estimated from switching at different circuit nodes and the capacitances associated with those nodes. However, for this method, detailed knowledge of the internal implementation of the circuit is required in order to obtain capacitances of circuit nodes. Moreover, the method has practical application only to circuits with a very regular structure, such as memory arrays. In the simulation method, a power model of the circuit is constructed from circuit simulations, the functions of which include switching activity, circuit state and the input vectors applied to the circuit. However, with an increase in the number of inputs and the complexity of today's circuits, the complexity of the process of creating such power macro models has increased exponentially. Although clustering can be used to reduce the complexity of power macro models, clustering is practical only for small circuit structures. Further, these techniques require substantial computation and storage resources.
An exceptionally high level of integration is possible in SOCs these days. However, due to the large size of the circuit and the computational complexity of the power estimation process, power estimation of real-world applications and workloads is not feasible at the gate-level or lower levels of abstraction. Previous work on instruction-based system-level power evaluation of SOC peripheral cores is based on power characterization of instructions or operations executed by the block. However, these prior art methods are applicable only to estimate average power of the blocks and cannot be used for cycle accurate power consumption of a block. Further, these methods do not provide a clear methodology for modeling power consumption of multiple overlapping operations, which is very common on complex blocks. It would be advantageous to be able to accurately estimate the power consumption of a circuit design without the need for excessive computational power and memory.